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ads8519 www.ti.com slas462d ? june 2007 ? revised september 2010 16-bit, 250ksps, serial, cmos, sampling analog-to-digital converter check for samples: ads8519 1 features description 23 ? 0v to 8.192v, 5v, and 10v input ranges the ads8519 is a complete 16-bit sampling analog-to-digital (a/d) converter using state-of-the-art ? 93db snr with 20khz input cmos structures. it contains a complete 16-bit, ? 1.5lsb max inl capacitor-based, successive approximation register ? 1lsb max dnl; 16 bits, no missing codes (sar) a/d converter with sample-and-hold, ? spi ? -compatible serial output with reference, clock, and a serial data interface. data can be output using the internal clock or synchronized to daisy-chain (tag) feature and 3-state bus an external data clock. the ads8519 also provides ? 5v analog supply, 1.65v to 5.25v i/o supply an output synchronization pulse for ease-of-use with ? pinout similar to 16-bit ads7809 (low-speed) standard dsp processors. and 12-bit ads7808 and ads8508 the ads8519 is specified at a 250ksps sampling ? no external precision resistors required rate over the full temperature range. internal precision ? uses internal or external reference resistors provide various input ranges including 10v, 5v, and 0v to 8.192v, while the innovative design ? 110mw typ power dissipation at 250ksps allows operation from a single 5v supply with power ? 28-pin ssop package dissipation under 125mw. ? simple dsp interface the ads8519 is available in a 28-pin ssop package, and is fully specified for operation over the applications industrial ? 40 c to +85 c temperature range. ? industrial process control ? data acquisition systems ? digital signal processing ? medical equipment ? instrumentation 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 spi is a trademark of motorola, inc. 3 all other trademarks are the property of their respective owners. production data information is current as of publication date. copyright ? 2007 ? 2010, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. successive approximation register clock comparator cs cdac buffer ref cap r1 in 25.67k w 7k w internal +4.096v ref 4k w serial data out and control busy dataclk data 2.87k w 7k w r2 in r3 in ext/int r/c sb/btc pwrd tag
ads8519 slas462d ? june 2007 ? revised september 2010 www.ti.com this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. package/ordering information (1) minimum no minimum specified inl missing sinad temperature package- package ordering transport product (lsb) codes (db) range lead designator number media, qty ads8519ibdb tube, 50 ads8519ib 1.5 16-bit 90 ? 40 c to +85 c ssop-28 db ads8519ibdbr tape and reel, 2000 ads8519idb tube, 50 ads8519i 3 15-bit 87 ? 40 c to +85 c ssop-28 db ads8519idbr tape and reel, 2000 (1) for the most current package and ordering information, see the package option addendum at the end of this document, or see the ti website at www.ti.com. absolute maximum ratings (1) (2) over operating free-air temperature range (unless otherwise noted). unit r1 in 25v r2 in 25v analog inputs r3 in 25v ref +v ana + 0.3v to agnd2 ? 0.3v dgnd, agnd2 0.3v ground voltage differences v ana 6v v dig 6v digital inputs ? 0.3v to +v dig + 0.3v internal power dissipation 700mw maximum junction temperature +165 c lead temperature (soldering, 10s) +300 c (1) stresses above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum conditions for extended periods may affect device reliability. (2) all voltage values are with respect to network ground terminal. electrical characteristics at t a = ? 40 c to +85 c, f s = 250ksps, and v dig = v ana = 5v, using internal reference (unless otherwise specified). ads8519i ads8519ib parameter test conditions min typ max min typ max unit resolution 16 16 bits analog input voltage ranges (1) impedance (1) capacitance 50 50 pf throughput speed conversion cycle time acquire and convert 4 4 m s throughput rate 250 250 ksps (1) 10v, 5v, 0v to 8.192v, etc. (see table 2 ) 2 submit documentation feedback copyright ? 2007 ? 2010, texas instruments incorporated product folder link(s): ads8519
ads8519 www.ti.com slas462d ? june 2007 ? revised september 2010 electrical characteristics (continued) at t a = ? 40 c to +85 c, f s = 250ksps, and v dig = v ana = 5v, using internal reference (unless otherwise specified). ads8519i ads8519ib parameter test conditions min typ max min typ max unit dc accuracy inl integral linearity error ? 3 3 ? 1.5 1.5 lsb (2) dnl differential linearity error ? 2 2 ? 1 1 lsb no missing codes 15 16 bits transition noise (3) 0.67 0.67 lsb 10v range internal reference ? 0.5 0.5 ? 0.25 0.25 full-scale %fsr error (4) (5) all other ranges internal reference ? 0.5 ? 0.05 0.5 ? 0.5 ? 0.05 0.5 full-scale error drift internal reference 7 7 ppm/ c 10v range external reference ? 0.05 0.003 0.05 ? 0.05 0.003 0.05 full-scale %fsr error (4) (5) all other ranges external reference ? 0.5 0.5 ? 0.5 0.5 full-scale error drift external reference 2 2 ppm/ c bipolar zero error (4) ? 4 4 ? 2 2 mv bipolar zero error drift 2 2 ppm/ c unipolar zero 8.192v ? 20 6 20 ? 20 6 20 mv error (4) unipolar zero error drift 0.4 0.4 ppm/ c recovery to rated accuracy after 1 m f capacitor to cap 1 1 ms power down power supply sensitivity +4.75v < v d < +5.25v ? 8 8 ? 8 8 lsb (v dig = v ana = v d ) ac accuracy sfdr spurious-free dynamic range f i = 20khz 95 100 97 100 db (6) thd total harmonic distortion f i = 20khz ? 96 ? 94 ? 98 ? 96 db f i = 20khz 87 91 90 92 db sinad signal-to-(noise+distortion) ? 60db input 30 32 db snr signal-to-noise ratio f i = 20khz 88 92 91 93 db full-power bandwidth (7) 500 500 khz sampling dynamics aperture delay 5 5 ns transient response fs step 2 2 m s overvoltage recovery (8) 150 150 ns reference internal reference voltage no load 4.076 4.096 4.116 4.076 4.096 4.116 v internal reference source current 1 1 m a (must use external buffer) internal reference drift 8 8 ppm/ c external reference voltage range 3.9 4.096 4.2 3.9 4.096 4.2 v for specified linearity external reference current drain external 4.096v ref. 100 100 m a (2) lsb means least significant bit. for the 10v input range, one lsb is 305 m v. (3) typical rms noise at worst-case transitions and temperatures. (4) as measured with circuit shown in figure 29 and figure 30 . (5) for bipolar input ranges, full-scale error is the worst case of ? full-scale or +full-scale uncalibrated deviation from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. for unipolar input ranges, full-scale error is the deviation of the last code transition divided by the transition voltage. it also includes the effect of offset error. (6) all specifications in db are referred to a full-scale 10v input. (7) full-power bandwidth is defined as the full-scale input frequency at which signal-to-(noise + distortion) degrades to 60db. (8) recovers to specified performance after 2 x fs input overvoltage. copyright ? 2007 ? 2010, texas instruments incorporated submit documentation feedback 3 product folder link(s): ads8519
ads8519 slas462d ? june 2007 ? revised september 2010 www.ti.com electrical characteristics (continued) at t a = ? 40 c to +85 c, f s = 250ksps, and v dig = v ana = 5v, using internal reference (unless otherwise specified). ads8519i ads8519ib parameter test conditions min typ max min typ max unit digital inputs logic levels v il low-level input voltage (9) v dig = 1.65v to 5.25v ? 0.3 0.6 ? 0.3 0.6 v v ih high-level input voltage (9) v dig = 1.65v to 5.25v 0.5 x v dig v dig + 0.3 0.5 x v dig v dig + 0.3 v i il low-level input current v il = 0v 10 10 m a i ih high-level input current v ih = 5v 10 10 m a digital outputs data format serial, 16-bits serial, 16-bits binary 2 ' s complement binary 2 ' s complement data coding or straight binary or straight binary conversion results only available conversion results only available pipeline delay after completed conversion after completed conversion selectable for internal selectable for internal data clock or external data clock or external data clock internal clock (output only when ext/ int low 9 9 mhz transmitting data) external clock (can run continually but not recommended ext/ int high 0.1 26 0.1 26 mhz for optimum performance) i sink = 1.6ma, v ol low-level output voltage 0.45 0.45 v v dig = 1.65v to 5.25v i source = 500 m a, v oh high-level output voltage v dig ? 0.45 v dig ? 0.45 v v dig = 1.65v to 5.25v hi-z state, leakage current 5 5 m a v out = 0v to v dig output capacitance hi-z state 15 15 pf power supplies v dig digital input voltage must be v ana 1.65 5.25 1.65 5.25 v v ana analog input voltage must be v ana 4.75 5 5.25 4.75 5 5.25 v i dig digital input current must be v ana 0.1 1 0.1 1 ma i ana analog input current must be v ana 22 25 22 25 ma power dissipation pwrd low f s = 250ksps 110 125 110 125 mw pwrd high 20 20 m w temperature range specified performance ? 40 +85 ? 40 +85 c derated performance (10) ? 55 +125 ? 55 +125 c storage ? 65 +150 ? 65 +150 c q ja thermal resistance 67 67 c/w (9) ttl-compatible at 5v supply. (10) the internal reference may not be started correctly beyond the industrial temperature range ( ? 40 c to +85 c); therefore, use of an external reference is recommended. 4 submit documentation feedback copyright ? 2007 ? 2010, texas instruments incorporated product folder link(s): ads8519
ads8519 www.ti.com slas462d ? june 2007 ? revised september 2010 pin configuration db package (top view) copyright ? 2007 ? 2010, texas instruments incorporated submit documentation feedback 5 product folder link(s): ads8519 v dig v ana busycs r/c nc tag nc data dataclk sync r1 in agnd1 nc cap agnd2 ncnc nc ref dgnd 12 3 4 5 6 7 8 9 10 11 12 13 14 2827 26 25 24 23 22 21 20 19 18 17 16 15 r2 in sb/btc ext/int pwrdnc nc r3 in
ads8519 slas462d ? june 2007 ? revised september 2010 www.ti.com pin assignments pin name no. i/o description agnd1 2 ? analog ground. used internally as ground reference point. minimal current flow. agnd2 9 ? analog ground busy output. falls when a conversion is started, and remains low until the conversion is completed and busy 25 o the data are latched into the output shift register. cs 24 ? chip select. internally ored with r/ c. cap 6 reference buffer capacitor, 2.2 m f tantalum capacitor to ground. serial data output. data are synchronized to dataclk, with the format determined by the level of sb/ btc. in the external clock mode, after 16 bits of data, the ads8519 outputs the level input on tag data 17 o as long as cs is low and r/ c is high (see figure 8 and figure 9 ). if ext/ int is low, data are valid on both the rising and falling edges of dataclk, and between conversions data stays at the level of the tag input when the conversion was started. either an input or an output, depending on the ext/ int level. output data are synchronized to this dataclk 16 i/o clock. if ext/ int is low, dataclk transmits 16 pulses after each conversion, and then remains low between conversions. dgnd 14 ? digital ground selects external or internal clock for transmitting data. if high, data are output synchronized to the ext/ int 13 ? clock input on dataclk. if low, a convert command initiates the transmission of the data from the previous conversion, along with 16 clock pulses output on dataclk. 5, 8, 10, 11, nc 18, 20, 22, ? not connected 23 power down input. if high, conversions are inhibited and power consumption is significantly reduced. pwrd 26 i results from the previous conversion are maintained in the output shift register. read/convert input. with cs low, a falling edge on r/ c puts the internal sample-and-hold into the hold state and starts a conversion. when ext/ int is low, this also initiates the transmission of the data r/ c 21 i results from the previous conversion. if ext/ int is high, a rising edge on r/ c with cs low, or a falling edge on cs with r/ c high, initiates the transmission of data from the previous conversion. reference input/output. outputs internal 4.096v reference. can also be driven by external system ref 7 i/o reference. in both cases, bypass to ground with a 2.2 m f tantalum capacitor. r1 in 1 i analog input. see table 2 for input range connections. r2 in 3 i analog input. see table 2 for input range connections. r3 in 4 i analog input. see table 2 for input range connections. select straight binary or binary two's complement data output format. if high, data are output in a sb/ btc 12 i straight binary format. if low, data are output in a binary two's complement format. sync output. this pin is used to supply a data synchronization pulse when the ext level is high and at sync 15 o least one external clock pulse has occurred when not in the read mode. see the external dataclk section for the external clock mode description. tag input for use in the external clock mode. if ext is high, digital data input from tag is output on tag 19 i data with a delay that depends on the external clock mode. see figure 8 and figure 9 . analog supply input. nominally +5v. connect directly to pin 20, and decouple to ground with 0.1 m f v ana 27 i ceramic and 10 m f tantalum capacitors. v dig 28 i digital supply input. connect directly to pin 19. 6 submit documentation feedback copyright ? 2007 ? 2010, texas instruments incorporated product folder link(s): ads8519
ads8519 www.ti.com slas462d ? june 2007 ? revised september 2010 timing requirements, t a = ? 40 c to +85 c parameter min typ max unit t w1 pulse duration, convert 40 ns t d1 delay time, busy from r/ c low 6 20 ns t w2 pulse duration, busy low 2.2 m s t d2 delay time, busy, after end of conversion 5 ns t d3 delay time, aperture 5 ns t conv conversion time 2.2 m s t acq acquisition time 1.8 m s t conv + t acq cycle time 4 m s t d4 delay time, r/ c low to internal dataclk output 270 ns t c1 cycle time, internal dataclk 110 ns t d5 delay time, data valid to internal dataclk high 15 35 ns t d6 delay time, data valid after internal dataclk low 20 35 ns t c2 cycle time, external dataclk 35 ns t w3 pulse duration, external dataclk high 15 ns t w4 pulse duration, external dataclk low 15 ns t su1 setup time, r/ c rise/fall to external dataclk high 15 ns t su2 setup time, r/ c transition to cs transition 10 ns t d7 delay time, sync, after external dataclk high 3 35 ns t d8 delay time, data valid from external dataclk high 2 13 ns t d9 delay time, cs rising edge to external dataclk rising edge 10 ns t d10 delay time, previous data available after cs, r/ c low 2 m s t su3 setup time, busy transition to first external dataclk 5 ns t d11 delay time, final external dataclk to busy rising edge 1 m s t su4 setup time, tag valid 0 ns t h1 hold time, tag valid 2 ns timing diagrams figure 1. critical timing copyright ? 2007 ? 2010, texas instruments incorporated submit documentation feedback 7 product folder link(s): ads8519 1 2 t su1 t su1 cs r/c external dataclk cs set low , discontinuous ext da taclk t su1 t su1 r/c cs external dataclk r/c set low , discontinuous ext da taclk t su2 t su2 cs r/c t su3 busy external dataclk cs set low , discontinuous ext da taclk setup t ime, r/c to cs
ads8519 slas462d ? june 2007 ? revised september 2010 www.ti.com timing diagrams (continued) figure 2. basic conversion timing: internal dataclk (read previous data during conversion) figure 3. basic conversion timing: external dataclk 8 submit documentation feedback copyright ? 2007 ? 2010, texas instruments incorporated product folder link(s): ads8519 r/c busy status (n+1) th accquisition (n+1) th conversion errorcorrection nth conversion errorcorrection internal dataclk (n?1) th conversion data data nth conversion data (n+2) th accquisition 1 2 16 2 16 d15 d0 d15 d0 t ag = 0 t ag = 0 t ag = 0 8 starts read cs , ext/int , and t ag are tied low t w1 t d1 t w2 t d3 t d11 t d2 t d3 t w1 t d1 t w2 t d11 t d2 t conv t acq t conv t acq t d4 t d4 t c1 t d5 t d6 1 busy status (n+1)th accquisition (n+1)th conversion errorcorrection nth conversion errorcorrection external dataclk data nth data (n+1)th data (n+2)th accquisition t ag = 0 no moredata to shift out no moredata to shift out t ag = 0 t ag = 0 t ag = 0 t ag = 0 r/c ext/int tied high, cs and t ag are tied low t w1 + t su1 starts read t w1 t w1 t d1 t w2 t d1 t w2 t d3 t d11 t d2 t d3 t d11 t d2 t su1 t conv t acq t conv t acq t su3 t su1 t su3 1 16 1 2 16 1 16 1 2 16
ads8519 www.ti.com slas462d ? june 2007 ? revised september 2010 timing diagrams (continued) figure 4. read after conversion (discontinuous external dataclk) figure 5. read during conversion (discontinuous external dataclk) copyright ? 2007 ? 2010, texas instruments incorporated submit documentation feedback 9 product folder link(s): ads8519 busy status (n+1) th accquisition error correction nth conversion external dataclk data nth conversion data sync = 0 d15 0 1 2 3 15 14 16 tag t01 d05 d10 d12 d13 d14 t00 t04 t03 t02 t13 t12 t11 t06 t16 t15 t14 tyy 5 4 11 12 13 10 d11 t05 d04 d03 d02 d01 txx t00 d00 null t17 null r/c ext/int tied high, cs tied low t w1 + t su1 starts read t w1 t d1 t w2 t su1 t d3 t d11 t d2 t conv t acq t d3 t d1 t su3 t w3 t c2 t w4 t su1 t d8 t d8 t su4 t h1 busy status errorcorrection nth conversion external dataclk data nth conversion data sync = 0 d15 0 1 2 3 15 14 16 d05 d10 d12 d13 d14 5 4 11 12 13 10 d11 d00 d04 d03 d02 d01 r/c ext/int tied high, cs and t ag tied low rising da t aclk change da t a, t w1 + t su1 starts read t ag is not recommended for this mode. there is not enough time to do so without violating t d11 . t w1 t d1 t w2 t d10 t d3 t su3 t conv t d2 t su1 t w3 t c2 t w4 t d11 t d8 t d8
ads8519 slas462d ? june 2007 ? revised september 2010 www.ti.com timing diagrams (continued) figure 6. read after conversion with sync (discontinuous external dataclk) figure 7. read during conversion with sync (discontinuous external dataclk) 10 submit documentation feedback copyright ? 2007 ? 2010, texas instruments incorporated product folder link(s): ads8519 busy status (n+1)th accquisition error correction nth conversion external dataclk data nth conversion data sync d15 2 3 4 5 17 16 18 tag t01 d05 d10 d12 d13 d14 t00 t04 t03 t02 t13 t12 t11 t06 t16 t15 t14 tyy t17 7 6 13 14 15 12 d11 t05 d00 d04 d03 d02 d01 txx =0 0 1 t00 null r/c ext/int tied high, cs tied low t w1 + t su1 starts read t w1 t su1 t su1 t d1 t d1 t d3 t d11 t d2 t w2 t d3 t conv t acq t su1 t su3 t c2 t w4 t w3 t c2 t d7 t d8 t su4 t h1 t d8 t su1 busy status errorcorrection nth conversion external dataclk data nth conversion data sync = 0 d15 2 3 4 5 17 16 18 d05 d10 d12 d13 d14 7 6 13 14 15 12 d11 d00 d04 d03 d02 d01 0 1 r/c ext/int tied high, cs and t ag tied low t w1 + t su1 starts read t ag is not recommended for this mode. there is not enough time to do so without violating t d11 . t w1 t w2 t d1 t d3 t d10 t su3 t su1 t su1 t w3 t d7 t c2 t d8 t c2 t w4 t su1 t d8 t d11 t conv t d2
ads8519 www.ti.com slas462d ? june 2007 ? revised september 2010 timing diagrams (continued) figure 8. conversion and read timing with continuous external dataclk (ext/ int tied high) read after conversions (not recommended) copyright ? 2007 ? 2010, texas instruments incorporated submit documentation feedback 11 product folder link(s): ads8519 0 1 2 3 4 17 18 bit 15 (msb) bit 14 bit 1 bit 0 (lsb) t ag 0 t ag 1 t ag 0 t ag 1 t ag 2 t ag 15 t ag 16 t ag 17 t ag 18 t ag 19 t c2 t w4 t w3 t w1 t su1 t su2 t d1 t su2 t c2 t d7 t d8 t d9 external dataclk cs r/c busy sync data tag
ads8519 slas462d ? june 2007 ? revised september 2010 www.ti.com timing diagrams (continued) figure 9. conversion and read timing with continuous external dataclk (ext/ int tied high) read previous conversion results during conversion (not recommended) 12 submit documentation feedback copyright ? 2007 ? 2010, texas instruments incorporated product folder link(s): ads8519 t c2 t w4 t w3 t w1 t su2 t su1 t d10 t d8 t d1 t su1 t c2 t d8 external dataclk cs r/c busy sync data tag bit 15 (msb) bit 0 (lsb) t ag 0 t ag 1 t ag 0 t ag 1 t ag 16 t ag 17 t ag 18 t ag 19
ads8519 www.ti.com slas462d ? june 2007 ? revised september 2010 typical characteristics supply current internal voltage reference vs vs histogram free-air temperature free-air temperature figure 10. figure 11. figure 12. bipolar zero error positive full-scale error negative full-scale error vs vs vs free-air temperature free-air temperature free-air temperature figure 13. figure 14. figure 15. positive full-scale error negative full-scale error spurious free dynamic range vs vs vs free-air temperature free-air temperature free-air temperature figure 16. figure 17. figure 18. copyright ? 2007 ? 2010, texas instruments incorporated submit documentation feedback 13 product folder link(s): ads8519 0 1000 2000 3000 4000 5000 6000 7000 8000 65530 65531 65532 65533 65534 code count 1 712 6930 547 2 4.09 4.092 4.094 4.096 4.098 4.1 4.102 4.104 -40 -20 0 20 40 60 80 t - free-air temperature - c a internal r voltage - v eference 15 16 17 18 19 20 21 22 23 24 25 -40 -20 0 20 40 60 80 t - free-air temperature - c a i - supply current - ma cc -5 -4 -3 -2 -1 0 1 2 3 4 5 -40 -20 0 20 40 60 80 internal reference 10v range t - free-air temperature - c a bpz - bipolar zero error - mv -0.25 -0.20 -0.15 -0.10 -0.05 0 0.05 0.10 0.15 0.20 0.25 -40 -20 0 20 40 60 80 pfse - positive full-scale error - %fsr internal reference10v range t - free-air temperature - c a nfse - negative full-scale error - %fsr -0.25 -0.20 -0.15 -0.10 -0.05 0 0.05 0.10 0.15 0.20 0.25 -40 -20 0 20 40 60 80 internal reference 10v range t - free-air temperature - c a -0.1 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08 0.1 -40 -20 0 20 40 60 80 pfse - positive full-scale error - %fsr t - free-air temperature - c a external reference10v range -0.1 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08 0.1 -40 -20 0 20 40 60 80 nfse - negative full-scale error - %fsr t - free-air temperature - c a external reference10v range 70 75 80 85 90 95 100 105 -40 -20 0 20 40 60 80 sfdr - spurious free dynamic range - db t - free-air temperature - c a f = 250ksps f = 20khz si
ads8519 slas462d ? june 2007 ? revised september 2010 www.ti.com typical characteristics (continued) signal-to-noise and total harmonic distortion signal-to-noise ratio distortion vs vs vs free-air temperature free-air temperature free-air temperature figure 19. figure 20. figure 21. signal-to-noise and distortion signal-to-noise ratio spurious free dynamic range vs vs vs input frequency input frequency input frequency figure 22. figure 23. figure 24. total harmonic distortion vs input frequency figure 25. 14 submit documentation feedback copyright ? 2007 ? 2010, texas instruments incorporated product folder link(s): ads8519 -100 -95-90 -85 -80 -75-70 -40 -20 0 20 40 60 80 thd - total harmonic distortion - db t - free-air temperature - c a f = 250ksps f = 20khz si 70 75 80 85 90 95 100 -40 t - free-air temperature - c a snr - signal-to-noise ratio - db -20 0 20 40 60 80 f = 250ksps f = 20khz si 70 75 80 85 90 95 100 -40 -20 0 20 40 60 80 f = 250ksps f = 20khz si snr - signal-to-noise and distortion - db t - free-air temperature - c a 70 75 80 85 90 95 100 1 10 100 1000 f - input frequency - khz i snr - signal-to-noise ratio - db 70 75 80 85 90 95 100 105 1 10 100 1000 sfdr - spurious free dynamic range - db f - input frequency - khz i 70 75 80 85 90 95 100 1 10 100 1000 f - input frequency - khz i sinad - signal-to-noise and distortion - db 70 75 80 85 90 95 100 105 1 10 100 1000 f - input frequency - khz i thd - total harmonic distortion - db
ads8519 www.ti.com slas462d ? june 2007 ? revised september 2010 typical characteristics (continued) inl figure 26. dnl figure 27. basic operation two signals control conversion in the ads8519: cs and r/ c. these two signals are internally ored together. to start a conversion, the chip must be selected ( cs low) and the conversion signal must be active (r/ c low). either signal can be brought low first. conversion starts on the falling edge of the second signal. busy goes low when conversion starts and returns high after the data from that conversion are shifted into the internal storage register. sampling begins when busy goes high. to reduce the number of control pins, cs can be tied low permanently. the r/ c pin then controls conversion and data reading exclusively. in the external clock mode, this configuration means that the ads8519 clocks out data whenever r/ c is brought high and the external clock is active. in the internal clock mode, data are clocked out every convert cycle, regardless of the states of cs and r/ c. the ads8519 provides a tag input for cascading multiple converters together. reading data the conversion result is available as soon as busy returns to high; therefore, data always represent the conversion previously completed, even when it is read during a conversion. the ads8519 outputs serial data in either straight binary or binary two ? s complement format. the sb/ btc pin controls the format. data are shifted out msb first. the first conversion immediately following a power-up does not produce a valid conversion result. data can be clocked out with either the internally-generated clock or with an external clock. the ext/ int pin controls this function. if an external clock is used, the tag input can be used to daisy-chain multiple ads8519 data pins together. copyright ? 2007 ? 2010, texas instruments incorporated submit documentation feedback 15 product folder link(s): ads8519 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 0 10000 20000 30000 40000 50000 60000 70000 code inl - lsbs -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 0 10000 20000 30000 40000 50000 60000 70000 code dnl - lsbs
ads8519 slas462d ? june 2007 ? revised september 2010 www.ti.com internal dataclk in the internal clock mode, data for the previous conversion are clocked out during each conversion period. the internal data clock is synchronized to the internal conversion clock so that it does not interfere with the conversion process. the dataclk pin becomes an output when ext/ int is low. 16 clock pulses are generated at the beginning of each conversion after timing t d4 is satisfied (that is, previous conversion results can only be read during the current conversion). dataclk returns to low when it is inactive. the 16 bits of serial data are shifted out of the data pin synchronous to this clock, with each bit available on a rising and then a falling edge. the data pin then returns to the state of the tag pin input sensed at the start of transmission. external dataclk the external clock mode offers several ways to retrieve conversion results. however, care must be taken to avoid corrupting the data because the external clock cannot be synchronized to the internal conversion clock. when ext/ int is set high, the r/ c and cs signals control the read state. when the read state is initiated, the result from the previously completed conversion is shifted out of the data pin synchronous to the external clock that is connected to the dataclk pin. each bit is available on a falling and then a rising edge. the maximum external clock speed of 28.5mhz allows data to be shifted out quickly either at the beginning of conversion or the beginning of sampling. there are several modes of operation available when using an external clock. it is recommended that the external clock run only while reading data. this mode is the discontinuous clock mode. because the external clock is not synchronized to the internal clock that controls conversion, slight changes in the external clock can cause conflicts that can corrupt the conversion process. specifications with a continuously running external clock cannot be ensured. it is especially important that the external clock does not run during the second half of the conversion cycle (approximately the time period specified by t d11 ; see the timing requirements table). in the discontinuous clock mode, data can be read during conversion or during sampling, with or without a sync pulse. data read during a conversion must meet the t d11 timing specification. data read during sampling must be complete before starting a conversion. whether reading during sampling or during conversion, a sync pulse is generated whenever at least one rising edge of the external clock occurs while the device is not in the read state. in the discontinuous external clock with sync mode, a sync pulse follows the first rising edge after the read command. data are shifted out after the sync pulse. the first rising clock edge after the read command generates a sync pulse. the sync pulse can be detected on the next falling edge and then the next rising edge. successively, each bit can be read first on the falling edge and then on the next rising edge. thus, 17 clock pulses after the read command are required to read on the falling edge; 18 clock pulses are necessary to read on the rising edge. if the clock is entirely inactive when not in the read state, no sync pulse is generated. in this case, the first rising clock edge shifts out the msb. the msb can be read on the first falling edge or on the next rising edge. in this discontinuous external clock with no sync mode, 16 clocks are necessary to read the data on the falling edge and 17 clocks for reading on the rising edge. data always represent the conversion already completed. table 1 summarizes the required dataclk pulses. table 1. dataclk pulses dataclk pulses required description with sync without sync read on falling edge of dataclk 17 16 read on rising edge of dataclk 18 17 16 submit documentation feedback copyright ? 2007 ? 2010, texas instruments incorporated product folder link(s): ads8519
ads8519 www.ti.com slas462d ? june 2007 ? revised september 2010 tag feature the tag feature allows the data from multiple ads8519 converters to be read on a single serial line. the converters are cascaded together using the data pins as outputs and the tag pins as inputs, as illustrated in figure 28 . the data pin of the last converter drives the processor serial data input. data are then shifted through each converter, synchronous to the externally supplied data clock, onto the serial data line. the internal clock cannot be used for this configuration. the preferred timing uses the discontinuous, external data clock during the sampling period. data must be read during the sampling period because there is not sufficient time to read data from multiple converters during a conversion period without violating the t d11 constraint (see external dataclk section). the sampling period must be sufficiently long to allow all data words to be read before starting a new conversion. in figure 28 , note that a null bit separates the data word from each converter. the state of the data pin at the end of a read cycle reflects the state of the tag pin at the start of the cycle. this condition is true in all read modes, including the internal clock mode. for example, when a single converter is used in the internal clock mode, the state of the tag pin determines the state of the data pin after all 16 bits have shifted out. when multiple converters are cascaded together, this state forms the null bit that separates the words. thus, with the tag pin of the first converter grounded as shown in figure 28 , the null bit becomes a zero between each data word. figure 28. timing of tag feature with single conversion (using external dataclk) copyright ? 2007 ? 2010, texas instruments incorporated submit documentation feedback 17 product folder link(s): ads8519 external dataclk . 2 3 4 35 34 36 17 16 20 21 19 1 null d q a00 d q null d q b00 d q a15 d q a16 d q b15 d q b16 d q tag(a) tag(b) data (a) data (b) dataclk ( both a & b) sync ( both a & b) ( both a & b) data ( b ) nth conversion data b15 a15 b00 b13 b14 b01 a00 a14 a13 a01 data ( a ) a15 a00 a13 a14 a01 18 nulla nullb nulla ads8519a tag data dataclk ads 8519b tag data dataclk processor sclk gpiogpio sdi t ag(a) = 0 t ag(a) = 0 r/c cs r/c cs r/c busy ext/int tied high, cs of both converter a and b, t ag input of converter a are tied low .
ads8519 slas462d ? june 2007 ? revised september 2010 www.ti.com analog inputs the ads8519 has three analog input ranges, as shown in table 2 . the offset specification is factory-calibrated with internal resistors. the gain specification is factory-calibrated with 0.1%, 0.25w, external resistors, as shown in figure 29 and figure 30 . the external resistors can be omitted if a larger gain error is acceptable or if using software calibration. the hardware trim circuitry shown in figure 29 and figure 30 can reduce the error to zero. table 2. input range connections (see figure 29 and figure 30 for complete information) analog input range connect r1 in to connect r2 in to connect r3 in to impedance 10v v in agnd cap 8.88k ? 10v agnd v in cap 8.88k ? 5v v in v in cap 6.08k ? 0v to 8.192v agnd agnd v in 5.95k ? figure 29. offset/gain circuits for unipolar input ranges 18 submit documentation feedback copyright ? 2007 ? 2010, texas instruments incorporated product folder link(s): ads8519 v in 2.2 m f 2.2 m f r1 in agnd1r2 in r3 in capref agnd2 v in r1 in agnd1r2 in r3 in cap refagnd2 + 5v 50 k w 2.2 m f 576k w input range 0v ? 8.192v without t rim with t rim (adjust gain) 2.2 m f
ads8519 www.ti.com slas462d ? june 2007 ? revised september 2010 figure 30. offset/gain circuits for bipolar input ranges analog input pins r1 in , r2 in , and r3 in have 25v overvoltage protection. the input signal must be referenced to agnd1. this referencing minimizes the ground-loop problem typical to analog designs. the analog input should be driven by a low-impedance source. a typical driving circuit using the opa627 or opa132 is shown in figure 30 . the ads8519 can operate with its internal 4.096v reference or an external reference. an external reference connected to pin 7 (ref) bypasses the internal reference. the external reference must drive the 4k ? resistor that separates pin 6 from the internal reference (see the illustration on page 1 ). the load varies with the difference between the internal and external reference voltages. the external reference voltage can vary from 3.9v to 4.2v. the internal reference is approximately 4.096v. the reference, whether internal or external, is buffered internally with the output on pin 6 (cap). the ads8519 is factory-tested with 2.2 m f capacitors connected to pin 6 (cap) and pin 7 (ref). each capacitor should be placed as close as possible to its pin. the capacitor on pin 7 band-limits the internal reference noise. a smaller capacitor can be used, but it may degrade snr and sinad the capacitor on pin 6 stabilizes the reference buffer and provides switching charge to the cdac during conversion. capacitors smaller than 1 m f may cause the buffer to become unstable and not hold sufficient charge for the cdac. the parts are tested to specifications with 2.2 m f, so larger capacitors are not necessary. the equivalent series resistance (esr) of these compensation capacitors is also critical. keep the total esr under 3 ? . see the typical characteristics section concerning how esr affects performance. copyright ? 2007 ? 2010, texas instruments incorporated submit documentation feedback 19 product folder link(s): ads8519 input range 10v 5v without t rim with t rim (adjust gain) r1 in agnd1r2 in r3 in capref agnd2 r1 in agnd1r2 in r3 in capref agnd2 v in 2.2 m f 2.2 m f 2.2 m f +5v 50k w 576k w 2.2 m f v in v in r1 in agnd1r2 in r3 in capref agnd2 r1 in agnd1r2 in r3 in capref agnd2 +5v 2.2 m f 2.2 m f 576k w 50k w v in 2.2 m f 2.2 m f
ads8519 slas462d ? june 2007 ? revised september 2010 www.ti.com neither the internal reference nor the buffer should be used to drive an external load. such loading can degrade performance. any load on the internal reference causes a voltage drop across the 4k ? resistor and affects gain. the internal buffer is capable of driving 2ma loads, but any load can cause perturbations of the reference at the cdac, degrading performance. it should be pointed out that, unlike other devices with a similar input structure, the ads8519 does not require a second high-speed amplifier used as a buffer to isolate the cap pin from the signal-dependent current in the r3 in pin, but can tolerate it if one does exist. the external reference voltage can vary from 3.9v to 4.2v. the reference voltage determines the size of the least significant bit (lsb). the larger reference voltages produce a larger lsb, which can improve snr. smaller reference voltages can degrade snr. figure 31. typical driving circuitry ( 10v, no trim) table 3. control truth table specific function cs r/ c busy ext/ int dataclk pwrd sb/ btc operation initiate conversion and 1 > 0 0 1 0 output 0 x initiates conversion n . data from conversion n - 1 output data using internal clocked out on data synchronized to 16 clock 0 1 > 0 1 0 output 0 x clock pulses output on dataclk. 1 > 0 0 1 1 input 0 x initiates conversion n . 0 1 > 0 1 1 input 0 x initiates conversion n . initiate conversion and outputs data with or without sync pulse. see the output data using external 1 > 0 1 1 1 input x x reading data section. clock 1 > 0 1 0 1 input 0 x outputs data with or without sync pulse. see reading data section. 0 0 > 1 0 1 input 0 x no actions 0 0 0 > 1 x x 0 x this is an acceptable condition. analog circuitry powered. conversion can x x x x x 0 x proceed.. power down analog circuitry disabled. data from previous x x x x x 1 x conversion maintained in output registers. serial data are output in binary twos complement x x x x x x 0 format. selecting output format x x x x x x 1 serial data are output in straight binary format. 20 submit documentation feedback copyright ? 2007 ? 2010, texas instruments incorporated product folder link(s): ads8519 opa627 gnd pin 1 pin 7 pin 2 pin 3 pin 4 pin 6 - 15 v +15 v v in 2.2 f m 100nf 2k w 22pf 2k w 22pf 2.2 f m 2.2 f m 100nf 2.2 f m r1 in agnd1r2 in r3 in capref ads8519 opa132 or agnd2 gnd gnd gnd gnd gnd gnd
ads8519 www.ti.com slas462d ? june 2007 ? revised september 2010 table 4. output codes and ideal input voltages description analog input range digital output binary twos complement straight binary full-scale range 10v 5v 0v to 8.192v (sb/btc low) (sb/btc high) least significant 305 m v 153 m v 125 m v bit (lsb) binary code hex code binary code hex code +full-scale 9.999695v 4.999847v 8.191875v 0111 1111 1111 1111 7fff 1111 1111 1111 1111 ffff (fs ? 1lsb) midscale 0v 0v 4.096v 0000 0000 0000 0000 0000 1000 0000 0000 0000 8000 one lsb below ? 305 m v 153 m v 4.095975v 1111 1111 1111 1111 ffff 0111 1111 1111 1111 7fff midscale ? full scale ? 10v ? 5v 0v 1000 0000 0000 0000 8000 0000 0000 0000 0000 0000 figure 32. gain adjust trim copyright ? 2007 ? 2010, texas instruments incorporated submit documentation feedback 21 product folder link(s): ads8519 12 7 6 9 agnd2 cap ref agnd1 r1 in +5v gain 12 7 6 9 agnd2 cap ref agnd1 r1 in 20k w 2.2 f m 30k w 10v (a) 10v with hardware trim (b) 10v without hardware trim 175k w 2.2 f m 2.2 f m 2.2 f m 10v
ads8519 slas462d ? june 2007 ? revised september 2010 www.ti.com revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from revision c (june, 2009) to revision d page ? changed input/output description for sb/ btc pin (pin 12) ................................................................................................... 6 changes from revision b (october, 2008) to revision c page ? changed external reference voltage range min value from 2.5v to 3.9v and max value from 4.1v to 4.2v ....................... 3 ? corrected pin names and numbers in paragraphs discussing internal and external reference operation and factory testing of device with 2.2 m f capacitors. .............................................................................................................................. 19 22 submit documentation feedback copyright ? 2007 ? 2010, texas instruments incorporated product folder link(s): ads8519
package option addendum www.ti.com 22-sep-2010 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ ball finish msl peak temp (3) samples (requires login) ads8519ibdb active ssop db 28 50 green (rohs & no sb/br) cu nipdau level-2-260c-1 year request free samples ads8519ibdbg4 active ssop db 28 50 green (rohs & no sb/br) cu nipdau level-2-260c-1 year request free samples ads8519ibdbr active ssop db 28 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year purchase samples ADS8519IBDBRG4 active ssop db 28 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year purchase samples ads8519idb active ssop db 28 50 green (rohs & no sb/br) cu nipdau level-2-260c-1 year request free samples ads8519idbg4 active ssop db 28 50 green (rohs & no sb/br) cu nipdau level-2-260c-1 year request free samples ads8519idbr active ssop db 28 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year purchase samples ads8519idbrg4 active ssop db 28 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year purchase samples (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature.
package option addendum www.ti.com 22-sep-2010 addendum-page 2 important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant ads8519ibdbr ssop db 28 2000 330.0 16.4 8.1 10.4 2.5 12.0 16.0 q1 ads8519idbr ssop db 28 2000 330.0 16.4 8.1 10.4 2.5 12.0 16.0 q1 package materials information www.ti.com 14-jul-2012 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) ads8519ibdbr ssop db 28 2000 367.0 367.0 38.0 ads8519idbr ssop db 28 2000 367.0 367.0 38.0 package materials information www.ti.com 14-jul-2012 pack materials-page 2
mechanical data msso002e ? january 1995 ? revised december 2001 post office box 655303 ? dallas, texas 75265 db (r-pdso-g**) plastic small-outline 4040065 /e 12/01 28 pins shown gage plane 8,20 7,40 0,55 0,95 0,25 38 12,90 12,30 28 10,50 24 8,50 seating plane 9,90 7,90 30 10,50 9,90 0,38 5,60 5,00 15 0,22 14 a 28 1 20 16 6,50 6,50 14 0,05 min 5,90 5,90 dim a max a min pins ** 2,00 max 6,90 7,50 0,65 m 0,15 0 ? 8 0,10 0,09 0,25 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0,15. d. falls within jedec mo-150
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